The present invention relates to methods of forming a semiconductor device, and more particularly, to methods of forming a semiconductor device including a fine pattern.
A semiconductor (integrated circuit) device generally includes a variety of types of patterns that are disposed on a semiconductor substrate and are electrically connected to each other to operate in a desired manner. Conventionally, the semiconductor patterns are generally defined using an exposure process. In such a process, a photoresist pattern is generally formed including openings at locations selected so that the exposure process defines the semiconductor pattern as a layer on the semiconductor substrate.
In a high integration semiconductor device, a line width (spacing between feature lines) that the exposure process may define has a limit. Particularly, a number of problems due to the exposure process may occur in light of semiconductor industry standards that requires a minimum line width of several tens of a nanometer. For instance, when a semiconductor pattern is defined using the exposure process, a uniformity of a line width of the semiconductor pattern may be degraded by a wafer region, a uniformity of exposure light and/or a uniformity of a lower portion layer. That is, a distribution of a line width of the semiconductor pattern may increase. As the integration density of semiconductor devices increase, a uniformity of a line width of the semiconductor pattern may be more severely degraded. Characteristics of the unit devices formed by the semiconductor pattern may become different (vary) due to the variation of the line width, which may cause a malfunction of the semiconductor device. For example, the variation of the line width may have a serious effect on a high integration memory device, where the same patterns are repeatedly arranged.
It may be more difficult to define a space between patterns having a fine line width than a pattern having a fine line width using the exposure process. To address this problem, a double exposure process has been introduced. In the typical double exposure process, first mask patterns of a large space are formed by a first exposure process and second mask patterns of a large space are formed between the first mask patterns by a second exposure process. However, the double exposure process may have a problem of a misalignment between the first and second mask patterns.